The present invention relates to a method for fabricating a MOS device on a SOS wafer by stabilizing the interface region with silicon and oxygen implantation.
Conventionally, a semiconductor device, e.g., an n-channel MOS transistor on an SOS wafer, is manufactured as follows.
As shown in FIG. 1A, a monocrystalline silicon layer 2 is formed by the epitaxial growth on a sapphire substrate 1 to a thickness of 0.6 .mu.m to prepare an SOS wafer. The silicon layer 2 was thermally oxidized, thus forming an SiO.sub.2 film (i.e., buffer film) 3 which is 500 .ANG. thick. CVD (chemical vapor deposition) was then carried out, thus forming on the SiO.sub.2 film 3 an Si.sub.3 N.sub.4 film which is 4500 .ANG. thick.
As shown in FIG. 1B, a resist pattern (not shown), having an opening corresponding to a prospective element isolation region, is formed by the photoengraving process (PEP) on the Si.sub.3 N.sub.4 film 4. The Si.sub.3 N.sub.4 film 4 and the SiO.sub.2 film 3 are sequentially etched by the reactive ion etching method (RIE method) using the resist pattern as a mask to form an SiO.sub.2 pattern 5 and an Si.sub.3 N.sub.4 pattern 6. The resist pattern is removed, and the resultant structure is selectively etched by an etching solution of potassium hydroxide and isopropyl alcohol using as masks the SiO.sub.2 pattern 5 and the Si.sub.3 N.sub.4 pattern 6, so an exposed portion of the silicon layer 2 is etched to a depth of 0.3 .mu.m.
As shown in FIG. 1C, the resultant structure is annealed in an atmosphere of a gas mixture of H.sub.2 and O.sub.2 at a temperature of 950.degree. C. for 6 hours to form a field oxide film (element isolation region) 7 having substantially the same level as that of the silicon layer 2. Therefore, an island silicon layer 8 (element region), isolated by the field oxide film 7, is formed.
As shown in FIG. 1D, after the Si.sub.3 N.sub.4 pattern 6 and the SiO.sub.2 pattern 5 are removed, the resultant structure is thermally oxidized to form a gate oxide film 9 on the island silicon layer 8 to a thickness of 450 .ANG.. After a resist pattern 10 having an opening corresponding to the prospective channel region is formed by PEP, a p-type impurity, e.g., boron, is ion-implanted in the island silicon layer 8 through the gate oxide film 9 at an acceleration energy of 160 keV and a dose of 3.times.10.sup.12 cm.sup.-2 using the resist pattern 10 as a mask, thereby forming a boron ion injection layer 11.
After the resist pattern 10 is removed, an impurity, e.g., phosphorus, doped polycrystalline (polysilicon) film is deposited by the CVD method to cover the entire surface to a thickness of 4,500 .ANG.. The polysilicon film is patterned to form a gate electrode 12, as shown in FIG. 1E.
As shown in FIG. 1F, an n-type impurity, e.g., arsenic, is ion-implanted in the island silicon layer 8 through the gate oxide film 9 at an acceleration energy of 40 keV and a dose of 2.times.10.sup.15 cm.sup.-2, using as masks the field oxide film 7 and the gate electrode 12. The resultant structure is then annealed to form n.sup.+ -type source and drain regions 13 and 14 in the silicon layer 8, so as to reach the surface of the sapphire substrate 1. In this case, the boron ion injection layer 11 is activated, so boron is diffused to form a p.sup.- -type channel region 15 in the silicon layer 8 between the source and drain regions 13 and 14.
As shown in FIG. 1G, an SiO.sub.2 film 16 and a boron-phosphorus-silicate-glass (BPSG) film 17 are sequentially formed by the CVD method. As shown in FIG. 1H, the BPSG film 17, the SiO.sub.2 film 16, and the gate oxide film 9 are selectively etched using a resist film (not shown) as a mask to form contact holes 18. Thereafter, the resist pattern is removed. An aluminum film is then deposited to cover the entire surface and is patterned to form aluminum wiring strips 19 and 20, which are respectively connected to the source and drain regions 13 and 14 through the corresponding contact holes 18. A phosphorus-silicate-glass (PSG) film 21 is deposited by the CVD method to cover the entire surface to a thickness of 1.2 .mu.m. Thus, an n-channel MOS transistor is prepared.
However, according to this conventional method, a crystal defect occurs at an interface between the sapphire substrate 1 and the silicon layer 2 (island silicon layer 8). For this reason, the conductivity type of a portion of the island silicon layer 8, which is located near the interface, is inverted, with the result that a current flows across the source and drain regions 13 and 14, which is called a back channel phenomenon. In addition, a large surface state occurs between the substrate 1 and island silicon layer 8. This surface state varies, inevitably varying the threshold voltage of the prepared transistor. In addition to these disadvantages, carrier mobility is lowered, which impairs high-speed operation of the MOS transistor. The crystal defect arises due to the following four reasons.
(1) Mismatching
The (100) plane of the monocrystalline silicon layer 2 grows on the (1102) plane of the sapphire substrate 1. Mismatching of about 12.5% of the crystal structues of sapphire and monocrystalline silicon occurs due to a difference between the crystal structures thereof.
(2) Influence of Sapphire Substrate
The silicon layer 2 is grown by epitaxial growth on the sapphire substrate 1 in an atmosphere of silane gas (SiH.sub.4), so that the following by-product reactions occur: EQU 2Si+Al.sub.2 O.sub.3 .fwdarw.Al.sub.2 O+2SiO EQU 2H.sub.2 +Al.sub.2 O.sub.3 .fwdarw.Al.sub.2 O+2H.sub.2 O
The main reaction is interfered with by the above by-product reactions.
(3) Stress
A thermal expansion coefficient of the sapphire substrate 1 is about twice that of the monocrystalline silicon layer 2. When the SOS wafer is abruptly cooled from a high-temperature state, the sapphire substrate 1 urges the silicon layer 2, thereby producing a stress. As a result, a crystal defect occurs in the silicon layer 2.
(4) Auto-doping of Aluminum
When the monocrystalline silicon layer 2 is epitaxially grown on the sapphire substrate 1, aluminum is automatically doped in the silicon layer 2 at a dose of 10.sup.21 to 10.sup.22 atoms/cm.sup.-3 (Trilhe J. et al., 4th Int. Conf. "Vapor Growth & Epitaxy", NAGOYA, PP. 65-66, 1977).
In consideration of these reasons, another method of manufacturing an n-channel MOS transistor, shown in FIG. 2, has been recently proposed wherein a monocrystalline silicon layer is epitaxially grown on a sapphire substrate 1, oxygen is ion-implanted in the vicinity of the interface of the substrate 1 and the silicon layer at an acceleration energy of 150 keV and a dose of 1.2.times.10.sup.16 cm.sup.-2. The resultant structure is annealed at a temperature of 1,150.degree. C. for 2 hours to prepare an SOS wafer, and the n-channel MOS transistor is prepared in the same manner as shown in FIGS. 1A to 1H. According to this method, a drain leakage current can be decreased to some extent, but aluminum oxide produced by the by-product reaction in item (2) cannot be effectively removed.
Still another conventional method is described in "Denshi Zairyo (Electronic Materials)", P. 115, January, 1981. According to this method, before silicon is epitaxially grown on sapphire, silicon and oxygen are ion-implanted in a sapphire substrate at a low acceleration energy and a dose of 1.times.10.sup.13 cm.sup.-2 to 5.times.10.sup.13 cm.sup.-2. Thereafter, silicon is epitaxially grown by the plasma CVD method at a low temperature of 800.degree. C. The content of aluminum in the monocrystalline silicon layer is decreased to 15% and 0.2% by ion implantation of silicon and oxygen, respectively. At the same time, electron mobility can be recovered to 65% and 75% of the bulk value by the ion implantation of silicon and oxygen, respectively. According to this method, although the content of aluminum can be decreased, the surface crystal structure is disturbed by the ion implantation. When the silicon layer is epitaxially grown on the sapphire substrate, mismatching of item (1) and stress of item (3) are increased. As a result, an inconvenient leak in the current increases.
Still another conventional method is proposed, wherein boron is ion-implanted in the island silicon layer to control the threshold voltage of the resultant transistor, and boron is also ion-implanted such that a peak of the impurity concentration occurs at the interface between the sapphire substrate and the island silicon layer. However, since the silicon layer becomes thin along with micropatterning of the element, it is very difficult to simultaneously control the impurity profiles in the vicinity of the surface of the silicon layer and at its interface with the sapphire substrate.